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Electronic Design Today
May 11, 2021
 
 
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Debugging and Optimization of a USB4 Logical Layer Link

Complexity of the USB4 Link, due to the 20-Gb/s signal rate and the need to bond for an aggregate 40 Gb/s, among other reasons, requires a coordinated plan to reach its full potential. Here’s a step-by-step methodology to achieve that goal.

 
 
 
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Arm said the Neoverse V1 core, previously code-named Zeus and part of its new V-Series of server CPU designs, is targeted at machine learning and HPC workloads in supercomputers.

 
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Tips & Tricks on Double-Pulse Testing

This application note describes the basic concept of double pulse testing, the necessary measurement setup and gives an overview of the parameters influencing the measurement. Furthermore, practical tips for carrying out the measurement are presented. At this point, the reader is referred to the software application included in the application note, which allows to easily perform double pulse tests with Rohde & Schwarz instruments. Learn More >>

 
 

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