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Electronic Design Update


Sponsored by Texas Instruments

Keys to quick success using high-speed data converters

Designing a test and measurement system? Our JESD204 Rapid Design IP, along with our high-speed data converter models and flexible evaluation boards, can help shorten design cycles and cut months of development time from your next project.

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See how to achieve a 12.8-GSPS sampling rate by utilizing interleaved RF-sampling ADCs.        

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JESD204 Rapid Design IP

The JESD204 Rapid Design IP enables FPGA engineers to achieve an accelerated path to a working JESD204 system. This resource is provided royalty free for use with TI high-speed data converters.

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Design a direct RF-sampling radar receiver

This design demonstrates a direct RF-sampling receiver for a radar operating in HF, VHF, UHF, L-, S-, C-, and part of X-band. See how to reduce the component count by eliminating several down-conversion stages and reduce overall system complexity.

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TI Precision Labs offers an easy-to-use video series covering the fundamentals of high-speed analog-to-digital converters.




System Design Considerations when Upgrading from JESD204B to JESD204C

This paper explores the major differences between JESD204B and JESD204C. Make an informed decision when choosing the best standard revision for your systems.

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Understanding S-parameters and why they matter

Learn how to use scattering parameters, also known as S-parameters, in the design of direct RF sampling architectures.

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